Learning Outcome

an ability to analyze and design computer logic circuits

Learning Objectives

1. compare and contrast three different signed number notations: sign and magnitude, diminished radix, and radix
2. convert a number from one signed notation to another
3. describe how to perform sign extension of a number represented using any of the three notation schemes
4. perform radix addition and subtraction
5. describe the various conditions of interest following an arithmetic operation: overflow, carry/borrow, negative, zero
6. describe the operation of a half-adder and write equations for its sum (S) and carry (C) outputs
7. describe the operation of a full adder and write equations for its sum (S) and carry (C) outputs
8. design a “population counting” or “vote counting” circuit using an array of half-adders and/or fulladders
9. design an N-digit radix adder/subtractor circuit with condition codes
10. design a (signed or unsigned) magnitude comparator circuit that determines if A=B, A<B, or A>B
11. describe the operation of a carry look-ahead (CLA) adder circuit, and compare its performance to that of a ripple adder circuit
12. define the CLA propagate (P) and generate (G) functions, and show how they can be realized using a half-adder
13. write the equation for the carry out function of an arbitrary CLA bit position
14. draw a diagram depicting the overall organization of a CLA
15. determine the worst case propagation delay incurred by a practical (PLD-based) realization of a CLA
16. describe how a “group ripple” adder can be constructed using N-bit CLA blocks
17. describe the operation of an unsigned multiplier array constructed using full adders
18. determine the full adder arrangement and organization (rows/diagonals) needed to construct an NxM-bit unsigned multiplier array
19. determine the worst case propagation delay incurred by a practical (PLD-based) realization of an NxM-bit unsigned multiplier array
20. describe the operation of a binary coded decimal (BCD) “correction circuit”
21. design a BCD full adder circuit
22. design a BCD N-digit radix (base 10) adder/subtractor circuit
23. define computer architecture, programming model, and instruction set
24. describe the top-down specification, bottom-up implementation strategy as it pertains to the design of a computer
25. describe the characteristics of a “two address machine”
26. describe the contents of memory: program, operands, results of calculations
27. describe the format and fields of a basic machine instruction (opcode and address)
28. describe the purpose/function of each basic machine instruction (LDA, STA, ADD, SUB, AND, HLT)
29. define what is meant by “assembly-level” instruction mnemonics
30. draw a diagram of a simple computer, showing the arrangement and interconnection of each functional block
31. trace the execution of a computer program, identifying each step of an instruction’s microsequence (fetch and execute cycles)
32. distinguish between synchronous and combinational system control signals
33. describe the operation of memory and the function of its control signals: MSL, MOE, and MWE
34. describe the operation of the program counter (PC) and the function of its control signals: ARS, PCC, and POA
35. describe the operation of the instruction register (IR) and the function of its control signals: IRL and IRA
36. describe the operation of the ALU and the function of its control signals: ALE, ALX, ALY, and AOE
37. describe the operation of the instruction decoder/microsequencer and derive the system control table
38. describe the basic hardware-imposed system timing constraints: only one device can drive a bus during a given machine cycle, and data cannot pass through more than one flip-flop (register) per cycle
39. discuss how the instruction register can be loaded with the contents of the memory location pointed to be the program counter and the program counter can be incremented on the same clock edge
40. modify a reference ALU design to perform different functions (e.g., shift and rotate)
41. describe how input/output instructions can be added to the base machine architecture
42. describe the operation of the I/O block and the function of its control signals: IOR and IOW
43. compare and contrast the operation of OUT instructions with and without a transparent latch as an integral part of the I/O block
44. compare and contrast “jump” and “branch” transfer-of-control instructions along with the architectural features needed to support them
45. distinguish conditional and unconditional branches
46. describe the basis for which a conditional branch is “taken” or “not taken”
47. describe the changes needed to the instruction decoder/microsequencer in order to dynamically change the number of instruction execute cycles based on the opcode
48. compare and contrast the machine’s asynchronous reset (“START”) with the synchronous state counter reset (“RST”)
49. describe the operation of a stack mechanism (LIFO queue)
50. describe the operation of the stack pointer (SP) register and the function of its control signals: ARS, SPI, SPD, SPA
51. compare and contrast the two possible stack conventions: SP pointing to the top stack item vs. SP pointing to the top stack item
52. describe how stack manipulation instructions (PSH/POP) can be added to the base machine architecture
53. discuss the consequences of having an unbalanced set of PSH and POP instructions in a given program
54. discuss the reasons for using a stack as a subroutine linkage mechanism: arbitrary nesting of subroutine calls, passing parameters to subroutines, recursion, and reentrancy
55. describe how subroutine linkage instructions (JSR/RTS) can be added to the base machine architecture
56. analyze the effect of changing the stack convention utilized (SP points to top stack item vs. next available location) on instruction cycle counts