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#draw a circuit for a bounce-free switch based on an S-R latch and analyze its behavior | #draw a circuit for a bounce-free switch based on an S-R latch and analyze its behavior | ||
#design a clocked synchronous state machine and verify its operation | #design a clocked synchronous state machine and verify its operation | ||
− | #define minimum risk and minimum cost state machine design strategies, and discuss the tradeoffs between | + | #define minimum risk and minimum cost state machine design strategies, and discuss the tradeoffs between the two approaches |
− | the two approaches | + | |
#compare state assignment strategy and state machine model choice (Mealy vs. Moore) with respect to PLD resources (P-terms and macrocells) required for realization | #compare state assignment strategy and state machine model choice (Mealy vs. Moore) with respect to PLD resources (P-terms and macrocells) required for realization | ||
#compare and contrast the operation of binary and shift register counters | #compare and contrast the operation of binary and shift register counters |
Revision as of 08:56, 21 August 2013
The Meyer Lectures on Digital Systems
Module 3: Sequential Logic Circuits
Objectives and Outcomes
© 2013
Learning Outcome
an ability to analyze and design sequential logic circuits
Learning Objectives
- describe the difference between a combinational logic circuit and a sequential logic circuit
- describe the difference between a feedback sequential circuit and a clocked synchronous state machine
- define the state of a sequential circuit
- define active high and active low as it pertains to clocking signals
- define clock frequency and duty cycle
- describe the operation of a bi-stable and analyze its behavior
- define metastability and illustrate how the existence of a metastable equilibrium point can lead to a random next state
- write present state – next state (PS-NS) equations that describes the behavior of a sequential circuit
- draw a state transition diagram that depicts the behavior of a sequential circuit
- construct a timing chart that depicts the behavior of a sequential circuit
- draw a circuit for a set-reset (“S-R”) latch and analyze its behavior
- discuss what is meant by “transparent” (or “data following”) in reference to the response of a latch
- draw a circuit for an edge-triggered data (“D”) flip-flop and analyze its behavior
- compare the response of a latch and a flip-flop to the same set of stimuli
- define setup and hold time and determine their nominal values from a timing chart
- determine the frequency and duty cycle of a clocking signal
- identify latch and flip-flop propagation delay paths and determine their values from a timing chart
- describe the operation of a toggle (“T”) flip-flop and analyze its behavior
- derive a characteristic equation for any type of latch or flip-flop
- identify the key elements of a clocked synchronous state machine: next state logic, state memory (flipflops), and output logic
- differentiate between Mealy and Moore model state machines, and draw a block diagram of each
- analyze a clocked synchronous state machine realized as either a Mealy or Moore model
- outline the steps required for state machine synthesis
- derive an excitation table for any type of flip-flop
- discuss reasons why formal state-minimization procedures are seldom used by experienced digital designers
- describe three ways that state machines can be specified in ABEL: using a clocked truth table, using clocked assignment operators, or using a state diagram approach
- list the ABEL attribute suffixes that pertain to sequential circuits
- draw a circuit for an oscillator and calculate its frequency of operation
- draw a circuit for a bounce-free switch based on an S-R latch and analyze its behavior
- design a clocked synchronous state machine and verify its operation
- define minimum risk and minimum cost state machine design strategies, and discuss the tradeoffs between the two approaches
- compare state assignment strategy and state machine model choice (Mealy vs. Moore) with respect to PLD resources (P-terms and macrocells) required for realization
- compare and contrast the operation of binary and shift register counters
- derive the next state equations for binary “up” and “down” counters
- describe the feedback necessary to make ring and Johnson counters self-correcting
- compare and contrast state decoding for binary and shift register counters
- describe why “glitches” occur in some state decoding strategies and discuss how to eliminate them
- identify states utilized by a sequence recognizer: accepting sequence, final, and trap
- determine the embedded binary sequence detected by a sequence recognizer