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| − | <font size="4">'''[[ECE_270_Digital_System_Design_Slecture_Wayner_Table_of_Contents|The | + | <font size="4">'''[[ECE_270_Digital_System_Design_Slecture_Wayner_Table_of_Contents|The Meyer Lectures on Digital Systems]]''' </font> |
'''Module 1: Boolean Algebra & CMOS logic structures''' | '''Module 1: Boolean Algebra & CMOS logic structures''' | ||
| − | Objectives and | + | Objectives and Outvomes |
[[slectures|Slectures]] by [[User:Rwayner|Robert Wayner]] | [[slectures|Slectures]] by [[User:Rwayner|Robert Wayner]] | ||
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---- | ---- | ||
| − | + | =Learning Outcome= | |
| + | An ability to analyze and design CMOS logic gates | ||
| + | =Learning Objectives= | ||
| + | #convert numbers from one base (radix) to another: 2, 10, 16 | ||
| + | #define a binary variable | ||
| + | #identify the theorems and postulates of switching algebra | ||
| + | #describe the principle of duality | ||
| + | #describe how to form a complement function | ||
| + | #prove the equivalence of two Boolean expressions using perfect induction | ||
| + | #describe the function and utility of basic electronic components (resistors, capacitors, diodes, MOSFETs) | ||
| + | #define the switching threshold of a logic gate and identify the voltage ranges typically associated with a “logic high” and a “logic low” | ||
| + | #define assertion level and describe the difference between a positive logic convention and a negative logic convention | ||
| + | #describe the operation of basic logic gates (NOT, NAND, NOR) constructed using N- and P-channel MOSFETs and draw their circuit diagrams | ||
| + | #define “fighting” among gate outputs wired together and describe its consequence | ||
| + | #define logic gate fan-in and describe the basis for its practical limit | ||
| + | #identifykeyinformationcontainedinalogicdevicedatasheet | ||
| + | #calculate the DC noise immunity margin of a logic circuit and describe the consequence of an insufficient margin | ||
| + | #describe the consequences of a “non-ideal” voltage applied to a logic gate input | ||
| + | #describehowunused(“spare”)CMOSinputsshouldbeterminated | ||
| + | #describe the relationship between logic gate output voltage swing and current sourcing/sinking capability | ||
| + | #describe the difference between “DC loads” and “CMOS loads” | ||
| + | #calculate VOL and VOH of a logic gate based on the “on” resistance of the active device and the amount of current sourced/sunk by the gate output | ||
| + | #calculate logic gate fan-out and identify a practical lower limit | ||
| + | #calculate the value of current limiting resistor needed for driving an LED | ||
| + | #describe the deleterious effects associated with loading a gate output beyond its rated specifications | ||
| + | #define propagation delay and list the factors that contribute to it | ||
| + | #define transition time and list the factors that contribute to it | ||
| + | #estimate the transition time of a CMOS gate output based on the “on” resistance of the active device and the capacitive load | ||
| + | #describe ways in which load capacitance can be minimized | ||
| + | #identify sources of dynamic power dissipation | ||
| + | #plot power dissipation of CMOS logic circuits as a function of operating frequency | ||
| + | #plot power dissipation of CMOS logic circuits as a function of power supply voltage | ||
| + | #describe the function and utility of decoupling capacitors | ||
| + | #define hysteresis and describe the operation of Schmitt-trigger inputs | ||
| + | #describe the operation and utility of a transmission gate | ||
| + | #define high-impedance state and describe the operation of a tri-state buffer | ||
| + | #define open drain as it applies to a CMOS logic gate output and calculate the value of pull-up resistor needed | ||
| + | #describe how to create “wired logic” functions using open drain logic gates | ||
| + | #calculate the value of pull-up resistor needed for an open drain logic gate | ||
---- | ---- | ||
Latest revision as of 07:36, 21 August 2013
The Meyer Lectures on Digital Systems
Module 1: Boolean Algebra & CMOS logic structures
Objectives and Outvomes
© 2013
Learning Outcome
An ability to analyze and design CMOS logic gates
Learning Objectives
- convert numbers from one base (radix) to another: 2, 10, 16
- define a binary variable
- identify the theorems and postulates of switching algebra
- describe the principle of duality
- describe how to form a complement function
- prove the equivalence of two Boolean expressions using perfect induction
- describe the function and utility of basic electronic components (resistors, capacitors, diodes, MOSFETs)
- define the switching threshold of a logic gate and identify the voltage ranges typically associated with a “logic high” and a “logic low”
- define assertion level and describe the difference between a positive logic convention and a negative logic convention
- describe the operation of basic logic gates (NOT, NAND, NOR) constructed using N- and P-channel MOSFETs and draw their circuit diagrams
- define “fighting” among gate outputs wired together and describe its consequence
- define logic gate fan-in and describe the basis for its practical limit
- identifykeyinformationcontainedinalogicdevicedatasheet
- calculate the DC noise immunity margin of a logic circuit and describe the consequence of an insufficient margin
- describe the consequences of a “non-ideal” voltage applied to a logic gate input
- describehowunused(“spare”)CMOSinputsshouldbeterminated
- describe the relationship between logic gate output voltage swing and current sourcing/sinking capability
- describe the difference between “DC loads” and “CMOS loads”
- calculate VOL and VOH of a logic gate based on the “on” resistance of the active device and the amount of current sourced/sunk by the gate output
- calculate logic gate fan-out and identify a practical lower limit
- calculate the value of current limiting resistor needed for driving an LED
- describe the deleterious effects associated with loading a gate output beyond its rated specifications
- define propagation delay and list the factors that contribute to it
- define transition time and list the factors that contribute to it
- estimate the transition time of a CMOS gate output based on the “on” resistance of the active device and the capacitive load
- describe ways in which load capacitance can be minimized
- identify sources of dynamic power dissipation
- plot power dissipation of CMOS logic circuits as a function of operating frequency
- plot power dissipation of CMOS logic circuits as a function of power supply voltage
- describe the function and utility of decoupling capacitors
- define hysteresis and describe the operation of Schmitt-trigger inputs
- describe the operation and utility of a transmission gate
- define high-impedance state and describe the operation of a tri-state buffer
- define open drain as it applies to a CMOS logic gate output and calculate the value of pull-up resistor needed
- describe how to create “wired logic” functions using open drain logic gates
- calculate the value of pull-up resistor needed for an open drain logic gate
