Latest revision as of 07:36, 21 August 2013

Learning Outcome

An ability to analyze and design CMOS logic gates

Learning Objectives

1. convert numbers from one base (radix) to another: 2, 10, 16
2. define a binary variable
3. identify the theorems and postulates of switching algebra
4. describe the principle of duality
5. describe how to form a complement function
6. prove the equivalence of two Boolean expressions using perfect induction
7. describe the function and utility of basic electronic components (resistors, capacitors, diodes, MOSFETs)
8. define the switching threshold of a logic gate and identify the voltage ranges typically associated with a “logic high” and a “logic low”
9. define assertion level and describe the difference between a positive logic convention and a negative logic convention
10. describe the operation of basic logic gates (NOT, NAND, NOR) constructed using N- and P-channel MOSFETs and draw their circuit diagrams
11. define “fighting” among gate outputs wired together and describe its consequence
12. define logic gate fan-in and describe the basis for its practical limit
13. identifykeyinformationcontainedinalogicdevicedatasheet
14. calculate the DC noise immunity margin of a logic circuit and describe the consequence of an insufficient margin
15. describe the consequences of a “non-ideal” voltage applied to a logic gate input
16. describehowunused(“spare”)CMOSinputsshouldbeterminated
17. describe the relationship between logic gate output voltage swing and current sourcing/sinking capability
18. describe the difference between “DC loads” and “CMOS loads”
19. calculate VOL and VOH of a logic gate based on the “on” resistance of the active device and the amount of current sourced/sunk by the gate output
20. calculate logic gate fan-out and identify a practical lower limit
21. calculate the value of current limiting resistor needed for driving an LED
22. describe the deleterious effects associated with loading a gate output beyond its rated specifications
23. define propagation delay and list the factors that contribute to it
24. define transition time and list the factors that contribute to it
25. estimate the transition time of a CMOS gate output based on the “on” resistance of the active device and the capacitive load
26. describe ways in which load capacitance can be minimized
27. identify sources of dynamic power dissipation
28. plot power dissipation of CMOS logic circuits as a function of operating frequency
29. plot power dissipation of CMOS logic circuits as a function of power supply voltage
30. describe the function and utility of decoupling capacitors
31. define hysteresis and describe the operation of Schmitt-trigger inputs
32. describe the operation and utility of a transmission gate
33. define high-impedance state and describe the operation of a tri-state buffer
34. define open drain as it applies to a CMOS logic gate output and calculate the value of pull-up resistor needed
35. describe how to create “wired logic” functions using open drain logic gates
36. calculate the value of pull-up resistor needed for an open drain logic gate