Learning Outcome

an ability to analyze and design sequential logic circuits

Learning Objectives

1. describe the difference between a combinational logic circuit and a sequential logic circuit
2. describe the difference between a feedback sequential circuit and a clocked synchronous state machine
3. define the state of a sequential circuit
4. define active high and active low as it pertains to clocking signals
5. define clock frequency and duty cycle
6. describe the operation of a bi-stable and analyze its behavior
7. define metastability and illustrate how the existence of a metastable equilibrium point can lead to a random next state
8. write present state – next state (PS-NS) equations that describes the behavior of a sequential circuit
9. draw a state transition diagram that depicts the behavior of a sequential circuit
10. construct a timing chart that depicts the behavior of a sequential circuit
11. draw a circuit for a set-reset (“S-R”) latch and analyze its behavior
12. discuss what is meant by “transparent” (or “data following”) in reference to the response of a latch
13. draw a circuit for an edge-triggered data (“D”) flip-flop and analyze its behavior
14. compare the response of a latch and a flip-flop to the same set of stimuli
15. define setup and hold time and determine their nominal values from a timing chart
16. determine the frequency and duty cycle of a clocking signal
17. identify latch and flip-flop propagation delay paths and determine their values from a timing chart
18. describe the operation of a toggle (“T”) flip-flop and analyze its behavior
19. derive a characteristic equation for any type of latch or flip-flop
20. identify the key elements of a clocked synchronous state machine: next state logic, state memory (flipflops), and output logic
21. differentiate between Mealy and Moore model state machines, and draw a block diagram of each
22. analyze a clocked synchronous state machine realized as either a Mealy or Moore model
23. outline the steps required for state machine synthesis
24. derive an excitation table for any type of flip-flop
25. discuss reasons why formal state-minimization procedures are seldom used by experienced digital designers
26. describe three ways that state machines can be specified in ABEL: using a clocked truth table, using clocked assignment operators, or using a state diagram approach
27. list the ABEL attribute suffixes that pertain to sequential circuits
28. draw a circuit for an oscillator and calculate its frequency of operation
29. draw a circuit for a bounce-free switch based on an S-R latch and analyze its behavior
30. design a clocked synchronous state machine and verify its operation
31. define minimum risk and minimum cost state machine design strategies, and discuss the tradeoffs between the two approaches
32. compare state assignment strategy and state machine model choice (Mealy vs. Moore) with respect to PLD resources (P-terms and macrocells) required for realization
33. compare and contrast the operation of binary and shift register counters
34. derive the next state equations for binary “up” and “down” counters
35. describe the feedback necessary to make ring and Johnson counters self-correcting
36. compare and contrast state decoding for binary and shift register counters
37. describe why “glitches” occur in some state decoding strategies and discuss how to eliminate them
38. identify states utilized by a sequence recognizer: accepting sequence, final, and trap
39. determine the embedded binary sequence detected by a sequence recognizer